The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a mask read only memory (ROM) capable of effectively reducing the distance between buried impurity diffusion regions.
As the level of integration of semiconductor devices increases, the scaling-down of a pattern pitch, i.e., decreasing of the size of a line/space of a circuit, becomes an important consideration. Such a decrease in the size of a line/space of a circuit is achieved by developing photolithography technologies. The line/space of a circuit is determined by various factors, e.g., the resolution power of a photoresist used for manufacturing a pattern or wavelength of light (shorter wavelengths are favorable for fine patterns). Decreasing the size of the line/space of circuits, i.e., decreasing their pitch, is very important to create more highly integrated semiconductor devices, and is a trend that is likely to become more important in the future.
As mentioned above, a semiconductor device can be reduced in size by decreasing the wavelength of light used during a photoresist process for manufacturing the device. This wavelength of light is one of the important factors that determines the resolution power of a photoresist used for a photolithography process. Recently, the light used for photolithography has been changed from g-line, which has a wavelength of 436 nm, to i-line, which has a wavelength of 365 nm. Also, it is understood that KrF excimer lasers, which has a wavelength of 248 nm, will be used in the future. In addition, the resolution power of a photolithography process increases as the aperture of an exposure device used during the photolithography is enlarged as well as when the wavelength of incident light decreases.
However, if the size of a semiconductor device is reduced by the above-mentioned method, investment costs for equipment capable of producing a new generation semiconductor device increase logarithmically. Such a high-cost investment in the high integration of semiconductor devices becomes a burden to a manufacturer. As a result, much attention has been devoted to developing a method capable of increasing the degree of integration of a device, while minimizing investment costs.
FIG. 1 is a plan view of a cell array region of a NOR type mask ROM, and FIGS. 2 through 5 are sectional views taken along lines II–II′, III–III′, IV-IV′ and V–V′, respectively, of FIG. 1.
In FIGS. 1 through 5, reference numeral 10 represents a semiconductor substrate, reference numeral 11 represents a buried impurity diffusion region, reference numeral 12 represents a gate insulation layer, reference numeral 14 represents a word line (i.e., gate electrode), reference numeral 16 represents an insulation layer for protecting the gate electrode, reference numeral 18 represents an interlayer dielectric (ILD) film, reference numeral 20 represents a metal interconnection, reference numeral 22 represents an insulation layer for protecting the metal interconnection, reference numeral 24 represents a channel region of a cell, which requires programming and into which impurities are implanted to control the threshold voltage of the channel region.
The buried impurity diffusion regions 11, which are parallel to each other, are separated by a first predetermined distance. The word lines 14, which are parallel to each other and are separated by a second predetermined distance, are arranged perpendicular to the buried impurity diffusion regions 11. The metal interconnections 20 are arranged on and parallel to the buried impurity diffusion regions 11. Impurities are implanted into the channel region 24 of a cell that requires programming. The buried impurity diffusion regions 11 act as a source/drain for a cell transistor and as bit lines.
Referring to FIG. 1, each cell transistor is formed along one of the word lines 14. Portions of the buried impurity diffusion region 11 that are overlapped by the word lines 14 become sources/drains, and portions between the buried impurity diffusion regions 11 that are below the word lines 14 become channel regions.
Also, in order to increase the degree of integration of a given mask ROM, it is important to reduce its cell transistor area. For the purpose of reducing the cell transistor area, the pitch of the buried impurity diffusion regions 11 (see FIG. 1) and the pitch of the word lines 14 (see FIG. 1) must be reduced. However, there are the following considerations in achieving this.
First, to reduce the pitch of the buried impurity diffusion regions 11, a decrease in the length of the channel regions should be considered. In other words, reducing the pitch of the buried impurity diffusion regions 11 by photolithography is permitted when the punch-through margin of a cell transistor can be secured. Meanwhile, to reduce the pitch of the word lines 14, a decrease in width of the channel region 24 should also be considered. In other words, even though the pitch of the word line 14 can be reduced by photolithography, a drop in drain current according to the decrease in width of the channel regions should also be considered.
Furthermore, a decrease in the drain current requires another design consideration, such as a need to sense the margin of the bit lines. Thus, if the punch-through margin of the cell transistors can be secured, reducing the pitch of the buried impurity diffusion regions 11 is preferred, which provides many design advantages.
FIGS. 6 through 8 are sectional views illustrating a conventional method for manufacturing a mask ROM having buried impurity diffusion regions.
As shown in FIG. 6, a field oxide layer 34 is formed in an isolation region (between a cell array region and a peripheral circuit region, and between a p-channel region and an n-channel region) of a semiconductor substrate 30 using a common isolation process. Then, a thin oxide layer 36 is grown over the semiconductor substrate 30, and a photoresist is deposited over these layers. The photoresist is then developed to form a photoresist pattern 38, which is required to form buried impurity diffusion regions. Impurity ions 40 are then implanted into the resultant structure, using the photoresist pattern 38 as a mask, to form buried impurity diffusion regions 42 in the cell array region. The photoresist pattern 38 is formed such that it completely covers the peripheral circuit region and exposes only regions of the cell array region that are for buried impurity diffusion regions 42.
In forming the buried impurity diffusion regions 42, which are to be sources/drains of cell transistors and bit lines, it is important to secure a punch-through margin as well as a minimum achievable pitch using the current photolithography technique. To this end, it is important to increase the distance between the buried impurity diffusion regions rather than to increase the size of the buried impurity diffusion regions 42.
As the design rule decreases for highly integrated devices, the size of a bar “B” of the photoresist pattern 38 (which determines the length of the channel regions)may decrease to be less than a desired size, as a result of various limitations in the photolithography technology. In other words, because of a low resolution in a 5 photolithography technique using the minimum design rule, undesirable photoresist residues may remain on the buried impurity diffusion regions 42. As a result, an over-exposure process is required to remove these photoresist residues. Therefore, the size of a space “S” (which determines the size of the buried impurity diffusion regions) may increase to greater than a desired size, as the size of the bar “B” decreases to less than a desired size.
In order to secure the distance between the buried impurity diffusion regions 42 for an appropriate punch-through margin, the size of the bar “B” cannot be less than a marginal size limited by the photolithography process. Thus, the marginal size of bar “B” may hinder the reduction of cell size.
Subsequently, as shown in FIG. 7, the photoresist patterns 38 (see FIG. 6) and the thin oxide layer 36 are removed, and then a sacrificial oxidation process is carried out, and a gate insulation layer 37 is formed. Word lines 44 are then formed in the cell array region and gates 48 of peripheral devices are formed in the peripheral circuit region (see FIG. 7).
Then, as shown in FIG. 8, a first insulation layer 56 is formed over the entire surface of the resultant structure, and electrodes 58 and 60, which contact impurity diffusion regions 42 and 57 of the peripheral devices, are formed. A second insulation layer 62 is then deposited over the resultant structure. In FIGS. 6 and 8, reference numeral 32 represents an N-well, reference numerals 46 and 50 represent capping layers, and reference numeral 52 represents spacers.
The distance between the buried impurity diffusion regions 42 required for an appropriate punch-through margin is restricted by over-diffusion of the buried impurity diffusion regions, as well as by the limitations of the photolithography technique as described above with reference to FIGS. 6 through 8. In particular, reducing the distance between the buried impurity diffusion regions 42 is hindered due to auto doping and oxidation enhanced diffusion (OED) in the buried impurity diffusion regions 42. Auto doping is defined as a spontaneous diffusion of the impurity diffusion regions 42 due to a difference in the activation rate of the impurities in the regions.
Referring to FIG. 6, the buried impurity diffusion regions 42 are formed before the formation of the gate insulation layer 37 and the word lines (i.e., gates) 44, so that the impurities in the buried impurity diffusion regions 42 diffuse into the channel region by heat energy supplied during a subsequent gate insulation layer formation this has the effect of reducing the length of the channel regions. In general, the activation rate of n-type impurities is lower than that of p-type impurities under the same conditions. However, when the n-type impurities are doped with a high concentration of 1015 ions/cm2, auto doping occurs in spite of its low activation rate. For example, in a buried impurity diffusion region doped with n-type impurities, diffusion of the n-type impurities into the channel region occurs by heat energy supplied during the formation of a gate insulation layer.
Also, in the conventional technique when the gate insulation layer 37 is formed after the formation of the buried impurity diffusion regions 42, OED occurs because of a segregation factor during the formation of the gate insulation layer 37. This facilitates the diffusion of the n-type impurities into the substrate. As a result, the buried impurity diffusion regions 42 doped with the n-type impurities may extend to the channel region.
The reason why there are two types of diffusion is that the buried impurity diffusion regions are formed prior to the formation of the gate insulation layer.